Dr. Hariharan has worked in several areas in Intel Corporation ranging from interconnect extraction tool development, aging and variation modelling for judicious guardband estimation for static timing analysis, graphics architecture modelling, and transistor compact modelling. He has had an occasion to work on the above areas in several Intel architectures like Broadwell, Skylake, Kabylake, Icelake, Tigerlake, etc, his area of work being especially on the technology and modelling side and dealing with process nodes like 22 nm, 14 nm, 10 nm and the more advanced nodes beyond that as also hybrid processes. Having worked in software development in a prior career, he brings to the table the best of device physics, software development and VLSI, and is keen to research in areas that require a synergy of all three areas, and also to impart his knowledge to young fertile minds and prepare them to be the future innovators of the world.

Educational Qualifications:

2008 PhD in Electrical Engineering IIT Bombay

2003 MS in Electrical Engineering Santa Clara University

1991 B.Tech in Electrical Engineering IIT Bombay

Teaching & Research Interests:

Dr Hariharan is interested in semiconductor device/compact modelling as well as interconnect modelling, especially the core physical principles that have gained prominence in the advanced process nodes in these fields. He also wishes to focus on ab-initio modelling, developing and implementing novel modelling capabilities in tools, and expose the students to modelling activities that up until now are generally glossed over, such as semiconductor band structure calculations, etc.