Network on Chip (NoC) architecture needed secured data processing and routing in multicore system on Chip (SoC). Sometime it becomes very difficult to provide secured network routing for physically access network. The performance of NoC architecture depends on switching techniques, routing scheme and topological structure. The paper proposed the chip implementation of the new technique of securing data in NoC routers. Many algorithms have been anticipated already for secured NoC routing but limited to their key size and block size. In the paper, NoC architecture is integrated with modified TACIT security algorithm on Virtex-5 FPGA. The key generation scheme is considered based on Hash function and distributed under 4 Hash function (4H) scheme. The greatest advantage of TACIT security algorithm is that the block size and key size both can be of 'n' bit. The design is developed for 'n' bit with the help of VHDL programming language in Xilinx ISE 14.2 and Modelsim 10.1 b software and synthesized for 512 and 1024 bit of block size on Virtex-5 FPGA. The design is optimized with the help of device utilization summary, timing parameters, maximum frequency and memory support. © 2015 The Authors. Published by Elsevier B.V.