The research article presents the design of five stage multistage telecommunication switching and FPGA synthesis. The cluster configuration of the designed network is 256 × 256 that supports maximum 3.436 × 10 10 calls simultaneously using 6,356,992 paths under the condition of full available network. Multistage switches are amenable to modular design and guarantees full available network. Modular design approach is used to build the large scale network, which can be fabricated easily using VLSI technology. The modular structure used to implement 256 × 256 five stage designs is 2 × 128 in first stage, 128 × 128 in second stage, 128 × 128 in third stage, 128 × 128 in fourth stage, and 128 × 2 in fifth stage. Moreover, the memory utilization has been found increased when number of nodes varied from 2 × 2 to 256 × 256 cluster size for the network. The design is developed with the help of Xilinx ISE 14.2 using VHDL, synthesized on Virtex-5 FPGA, and function simulation is carried out in Modelsim 10.1b student edition. The experimental set up ensures the successful transmission of data among inlets/outlets of the developed five stage network chip. © 2017, Springer Science+Business Media, LLC.