In this paper, an efficient implementation of the concurrent decision feedback equalizer (DFE) is carried out using offset binary coding (OBC) based on distributed arithmetic (DA). The concurrent decision feedback equalizer is employed in multi-gigabit systems which uses the principle of parallelization. However, the hardware complexity of adders and multipliers rises quadratically with parallelization factor. In our proposed technique, we have used look-up table (LUT) and shift-accumulate block as per DA requirement. In order to reduce the access time of LUT, we employed OBC scheme which therefore improves the speed of filtering operation. Moreover, it also reduces the chip area for LUT based filter design. Furthermore, our design provides significant reduction of hardware complexities in spite of slight increase in address decoding logic of OBC combinations while LUT complexity grows linearly. By doing so, the concurrent nature of look-ahead DFE is unaltered and can still be used for multi-gigabit applications. We have estimated hardware complexity and critical path of our design and compared with best existing schemes. Synthesis is performed in UMC 180 nm CMOS technology using cadence RTL compiler for the feedback filter length N = 4, 6 and 8. The proposed structure of concurrent look-ahead DFE is found to have low area in comparison to other schemes for any length of the feedback filter. © 2016 IEEE.