In this paper, we design a single transistor and zero-capacitor dynamic random access memory (DRAM or ZRAM) using band-gap engineered silicon-germanium (SiGe) Junctionless Double Gate Field Effect Transistor (JL-DGFET) device structure through 2D Sentaurus TCAD numerical simulations. We see that the inadequate charge storage capability of silicon-based 1T-DRAM is the main reason for short retention time. However, our simulations show that the performance can be further improved by replacing silicon substrate with silicon-germanium material. Moreover, a reduced breakdown voltage and hysteresis IDS-VDS characteristics are observed by putting SiGe as a bulk. Furthermore, the thickness of oxide and bulk material, and doping concentration are varied and their impacts are shown on the hysteresis output characteristic. High value of bipolar gain (β) is attained in designed band-gap engineered Si(1-x)Gex JL-DGFET transistors, which can be employed for enhancement of sensing margin in dynamic memories. © 2015 IEEE.