Critical Read Stability (TREAD) and Critical Writeability (TWRITE) are two SRAM metrics which can characterize the dynamic behavior of read and write operations. In this paper, the impact of NBTI on TREAD and TWRITE is shown. Worst-case use conditions are identified by varying the relative degradation of the two p-FETs. Monte-Carlo simulations using foundry models (High-k Metal Gate planar MOSFET) are performed to analyze time-zero variability for different use conditions. The dynamic metrics TREAD and TWRITE are correlated with static metrics SVNM and BWTV respectively for worst-case use conditions. Degradation trend of TREAD and TWRITE is then discussed for worst and symmetric NBTI degradation cases by varying ΔVTH. © 2018 IEEE.

Sonal Singhal

Electrical Engineering

(SoE) School of Engineering

Babu S.J.

Chaudhari S.P.

Goel N.

<p>Shiv Nadar University is a comprehensive, multidisciplinary, research-focused, and student-centric University offering a full range of academic programs at the undergraduate, postgraduate and doctoral level. With state-of-the-art infrastructure, the University comprises of academic wings, sophisticated labs, international standard sports facilities, amphitheaters, auditorium, conference rooms and smart classrooms. The University&rsquo;s goal is to become internationally recognized for the quality of its research and creative endeavors and their applicability to improving quality of life, generating new insights and expanding the boundaries of human knowledge creativity. Committed to excellence in teaching, research and service, the University aims to serve the higher education needs of India and the world beyond.</p>

Shiv Nadar University

Analyzing Impact of NBTI and Time-Zero Variability on Dynamic SRAM Metrics

INDICON 2018 - 15th IEEE India Council International Conference

Continuous scaling of CMOS technology has led to reliability issues and process variability that affect the circuit performance of the SRAM cell. The dynamic behavior of SRAM cells are characterized by critical read-stability (Tread) and critical write-ability (Twrite) while the Static Noise Margins (SNMs) are deduced by the static metrics that are the key performance metrics. The work in this paper demonstrates the cumulative impact of process variability and Negative Bias Temperature Instability (NBTI) degradation on the dynamic metrics of the SRAM cell under varied temperature conditions. Degradation due to NBTI is incorporated by considering different activity factors (α) for the dynamic metrics. Time-zero or process variability is performed for fresh-case, symmetric and asymmetric degradation by Monte Carlo run simulations using foundry models in addition to examining the effect of correlation with their corresponding static metrics. © Springer Nature Singapore Pte Ltd 2020.

Lecture Notes in Electrical Engineering

Analyzing the impact of nbti and process variability on dynamic sram metrics under temperature variations

Static metrics are often used to characterize read stability and write-ability of an SRAM cell. In this paper, two major dynamic SRAM metrics: critical read stability (TREAD) and critical writeability (TWRITE) are discussed and correlated with static metrics. For correlation between dynamic and static metrics, variability analysis is carried out at time-zero and after NBTI degradation of the SRAM cell. Shift in correlation factor is compared for before and after NBTI degradation. Assessment of correlation between dynamic and static metrics is used to identify those static metrics which best capture the dynamic behavior of the cell. © 2018 IEEE.

Proceedings - 2018 IEEE 4th International Symposium on Smart Electronic Systems, iSES 2018

Correlation of dynamic and static metrics of SRAM cell under time-zero variability and after NBTI degradation

Microelectronics Reliability

Impact and mitigation of SRAM read path aging

Time-zero-variability and BTI impact on advanced FinFET device and circuit reliability

Degradation in planar high-k metal gate pand n-channel MOSFETs, respectively, under negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) stress is studied using different characterization methods. Ultrafast measure stress measure (UF-MSM) method with a measurement delay of a few microseconds is used to characterize the threshold voltage shift (ΔVT). Gated-diode or direct current IV is used to directly estimate the trap generation (TG) during BTI, after correcting for the measurement inconsistencies. BTI experiments are performed under DC stress at different stress bias (VG-STR) and temperature (T) values also under AC stress at different pulse duty cycle (PDC) and frequency (f) values. Measured ΔVT as well as TG show remarkable similarities between NBTI and PBTI stress, under both DC and AC stress. It is shown that TG dominates NBTI and PBTI degradation under both DC and AC stress. © 1963-2012 IEEE.

IEEE Transactions on Electron Devices

A Comparative Study of NBTI and PBTI Using Different Experimental Techniques

BSIM-CMG based HSPICE framework is developed for simulating time-zero and Negative Bias Temperature Instability (NBTI) variability of SRAM performance parameters. Time-zero variability of Read Static Noise Margin, Hold Static Noise Margin and Flip-Time for different process corners are simulated. Models used for SPICE simulation are foundry qualified sub-20nm FinFET for two types of 6T SRAM cells, HighSpeed and High-Density cells. The Impact of stochastic BTI for DC and AC activity stress on these parameters are studied for relevant worst-case process corner. The impact of Vdd reduction on time-zero and post-BTI SRAM parameter variability is also studied. Critical failure situations are identified. © 2015 IEEE.