This paper presents novel capacitor less dynamic random access memory (DRAM) cells through band-gap engineered silicon-germanium (SiGe) junction less double gate field effect transistor (JL-DGFET) using two-dimensional commercial TCAD device simulator. The design window of capacitor less DRAM cell and its operations have been described. We observe hysteresis current-voltage characteristic and steep change in sub-threshold slope (SS) in SiGe JL-DGFET. The correlation between the IDS - VGS and IDS - VDS characteristics of the device during different operation of memory cells are discussed. Furthermore, high value of bipolar gain (i.e. β) is observed in optimally designed SiGe JL-DGFET transistors, which can be utilized for the improvement of sensing margin in dynamic memories. The results presented in this paper can provide an opportunity for future DRAM design in deep nanometer technology. © 2016 IEEE.