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SHEAR SORT: A TRUE TWO-DIMENSIONAL SORTING TECHNIQUE FOR VLSI NETWORKS.
Isaac Scherson D., , Adi Shamir
Published in IEEE, New York, NY, USA
1986
Pages: 903 - 908
Abstract
Given a sequence of numbers which can be mapped into an m multiplied by n array, sorting rows and columns is shown to yield an overall sorted sequence. This unusually simple procedure is shown to require O(log//2 m) iterations by analyzing the data movement in the array under successive row and column sorts. An efficient bubble sort network suitable for VLSI implementation, with near-optimal area-time**2 performance, is a direct application of the row-column sorting technique. The ease of implementation for practical VLSI chips is also demonstrated.
About the journal
Published in IEEE, New York, NY, USA
Open Access
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