Flexible and low-power consuming integrated circuits are some of the basic requirements for smart wearable devices. High mobility solution-processed organic field-effect transistors (OFETs) have the potential to make a big impact in printed electronic circuits, but their overall performance is currently limited by unusually high threshold voltages (Vth). Herein, systematic optimization of donor–acceptor conjugated polymer, based on dithienothiophene (DTT) and thiophene-flanked diketopyrrolopyrrole (DPP), namely, PDPPT–DTT, OFETs by application of self-assembled monolayers (SAMs) at the semiconductor–dielectric, and semiconductor–metal interfaces is reported. The results clearly exhibit that simultaneous application of octyltrichlorosilane (OTS) as semiconductor–dielectric interface modifying layer and pentafluorobenzene thiol (PFBT) as semiconductor–metal interface modifying layer results in significantly lower Vth and subthreshold slope values from −14.07 V and 13.26 (V Dec−1) to +1.06 V and 7.11 (V Dec−1), respectively. This tailored approach is also beneficial in enhancing hole mobility values by an order of magnitude from 0.01 to 0.5 cm2 V−1 s−1 along with the possibility of switching from hole accumulation mode (Vth = −3.75 V) to depletion mode (Vth = +1.06 V) through device engineering. Simultaneous interface engineering reveals OFET electronic properties can be fine-tuned for robust circuits and low power electronic applications. © 2020 Wiley-VCH GmbH