The aim of the work is to design and implement a low power 32 bits RISC core on Xilinx Nexys 4 FPGA. We also look at the further reducing the dynamic power consumption by implementing a shared RAM dual core design and take advantage of parallelism offered by FPGAs to run two cores simultaneously. The design is based on 5-stage pipelined DLX architecture. The DLX architecture in a RISC core consists of Fetch, Decode, Execute, Memory access and Write-back cycle. The core is designed using Verilog HDL. The standard low power single core design consumes 0.098W at 100MHz frequency. The shared RAM dual core design consumes 0.101W at 100MHz clock frequency. For this design we also code an assembler to convert Assembly language to machine code in python. © 2018 IEEE.